/************************************************************************************************/
/*                                                                                              */
/*  Copyright 2010  Broadcom Corporation                                                        */
/*                                                                                              */
/*     Unless you and Broadcom execute a separate written software license agreement governing  */
/*     use of this software, this software is licensed to you under the terms of the GNU        */
/*     General Public License version 2 (the GPL), available at                                 */
/*                                                                                              */
/*          http://www.broadcom.com/licenses/GPLv2.php                                          */
/*                                                                                              */
/*     with the following added to such license:                                                */
/*                                                                                              */
/*     As a special exception, the copyright holders of this software give you permission to    */
/*     link this software with independent modules, and to copy and distribute the resulting    */
/*     executable under terms of your choice, provided that you also meet, for each linked      */
/*     independent module, the terms and conditions of the license of that module.              */
/*     An independent module is a module which is not derived from this software.  The special  */
/*     exception does not apply to any modifications of the software.                           */
/*                                                                                              */
/*     Notwithstanding the above, under no circumstances may you combine this software in any   */
/*     way with any other Broadcom software provided under a license other than the GPL,        */
/*     without Broadcom's express prior written consent.                                        */
/*                                                                                              */
/************************************************************************************************/

#ifndef __BRCM_RDB_EMMCSDXC_H__
#define __BRCM_RDB_EMMCSDXC_H__

#define EMMCSDXC_SYSADDR_OFFSET                                           0x00000000
#define EMMCSDXC_SYSADDR_TYPE                                             UInt32
#define EMMCSDXC_SYSADDR_RESERVED_MASK                                    0x00000000
#define    EMMCSDXC_SYSADDR_SYSADDR_SHIFT                                 0
#define    EMMCSDXC_SYSADDR_SYSADDR_MASK                                  0xFFFFFFFF

#define EMMCSDXC_BLOCK_OFFSET                                             0x00000004
#define EMMCSDXC_BLOCK_TYPE                                               UInt32
#define EMMCSDXC_BLOCK_RESERVED_MASK                                      0x00000000
#define    EMMCSDXC_BLOCK_BCNT_SHIFT                                      16
#define    EMMCSDXC_BLOCK_BCNT_MASK                                       0xFFFF0000
#define    EMMCSDXC_BLOCK_TBS_12_SHIFT                                    15
#define    EMMCSDXC_BLOCK_TBS_12_MASK                                     0x00008000
#define    EMMCSDXC_BLOCK_HSBS_SHIFT                                      12
#define    EMMCSDXC_BLOCK_HSBS_MASK                                       0x00007000
#define    EMMCSDXC_BLOCK_TBS_SHIFT                                       0
#define    EMMCSDXC_BLOCK_TBS_MASK                                        0x00000FFF

#define EMMCSDXC_ARG_OFFSET                                               0x00000008
#define EMMCSDXC_ARG_TYPE                                                 UInt32
#define EMMCSDXC_ARG_RESERVED_MASK                                        0x00000000
#define    EMMCSDXC_ARG_ARG_SHIFT                                         0
#define    EMMCSDXC_ARG_ARG_MASK                                          0xFFFFFFFF

#define EMMCSDXC_CMD_OFFSET                                               0x0000000C
#define EMMCSDXC_CMD_TYPE                                                 UInt32
#define EMMCSDXC_CMD_RESERVED_MASK                                        0xC004FFC0
#define    EMMCSDXC_CMD_CIDX_SHIFT                                        24
#define    EMMCSDXC_CMD_CIDX_MASK                                         0x3F000000
#define    EMMCSDXC_CMD_CTYP_SHIFT                                        22
#define    EMMCSDXC_CMD_CTYP_MASK                                         0x00C00000
#define    EMMCSDXC_CMD_DPS_SHIFT                                         21
#define    EMMCSDXC_CMD_DPS_MASK                                          0x00200000
#define    EMMCSDXC_CMD_CCHK_EN_SHIFT                                     20
#define    EMMCSDXC_CMD_CCHK_EN_MASK                                      0x00100000
#define    EMMCSDXC_CMD_CRC_EN_SHIFT                                      19
#define    EMMCSDXC_CMD_CRC_EN_MASK                                       0x00080000
#define    EMMCSDXC_CMD_RTSEL_SHIFT                                       16
#define    EMMCSDXC_CMD_RTSEL_MASK                                        0x00030000
#define    EMMCSDXC_CMD_MSBS_SHIFT                                        5
#define    EMMCSDXC_CMD_MSBS_MASK                                         0x00000020
#define    EMMCSDXC_CMD_DTDS_SHIFT                                        4
#define    EMMCSDXC_CMD_DTDS_MASK                                         0x00000010
#define    EMMCSDXC_CMD_ACMDEN_SHIFT                                      2
#define    EMMCSDXC_CMD_ACMDEN_MASK                                       0x0000000C
#define    EMMCSDXC_CMD_BCEN_SHIFT                                        1
#define    EMMCSDXC_CMD_BCEN_MASK                                         0x00000002
#define    EMMCSDXC_CMD_DMA_SHIFT                                         0
#define    EMMCSDXC_CMD_DMA_MASK                                          0x00000001

#define EMMCSDXC_RESP0_OFFSET                                             0x00000010
#define EMMCSDXC_RESP0_TYPE                                               UInt32
#define EMMCSDXC_RESP0_RESERVED_MASK                                      0x00000000
#define    EMMCSDXC_RESP0_RESP0_SHIFT                                     0
#define    EMMCSDXC_RESP0_RESP0_MASK                                      0xFFFFFFFF

#define EMMCSDXC_RESP2_OFFSET                                             0x00000014
#define EMMCSDXC_RESP2_TYPE                                               UInt32
#define EMMCSDXC_RESP2_RESERVED_MASK                                      0x00000000
#define    EMMCSDXC_RESP2_RESP2_SHIFT                                     0
#define    EMMCSDXC_RESP2_RESP2_MASK                                      0xFFFFFFFF

#define EMMCSDXC_RESP4_OFFSET                                             0x00000018
#define EMMCSDXC_RESP4_TYPE                                               UInt32
#define EMMCSDXC_RESP4_RESERVED_MASK                                      0x00000000
#define    EMMCSDXC_RESP4_RESP4_SHIFT                                     0
#define    EMMCSDXC_RESP4_RESP4_MASK                                      0xFFFFFFFF

#define EMMCSDXC_RESP6_OFFSET                                             0x0000001C
#define EMMCSDXC_RESP6_TYPE                                               UInt32
#define EMMCSDXC_RESP6_RESERVED_MASK                                      0x00000000
#define    EMMCSDXC_RESP6_RESP6_SHIFT                                     0
#define    EMMCSDXC_RESP6_RESP6_MASK                                      0xFFFFFFFF

#define EMMCSDXC_BUFDAT_OFFSET                                            0x00000020
#define EMMCSDXC_BUFDAT_TYPE                                              UInt32
#define EMMCSDXC_BUFDAT_RESERVED_MASK                                     0x00000000
#define    EMMCSDXC_BUFDAT_BUFDAT_SHIFT                                   0
#define    EMMCSDXC_BUFDAT_BUFDAT_MASK                                    0xFFFFFFFF

#define EMMCSDXC_PSTATE_OFFSET                                            0x00000024
#define EMMCSDXC_PSTATE_TYPE                                              UInt32
#define EMMCSDXC_PSTATE_RESERVED_MASK                                     0xE000F0F0
#define    EMMCSDXC_PSTATE_DLS7_4_SHIFT                                   25
#define    EMMCSDXC_PSTATE_DLS7_4_MASK                                    0x1E000000
#define    EMMCSDXC_PSTATE_CLSL_SHIFT                                     24
#define    EMMCSDXC_PSTATE_CLSL_MASK                                      0x01000000
#define    EMMCSDXC_PSTATE_DLS3_0_SHIFT                                   20
#define    EMMCSDXC_PSTATE_DLS3_0_MASK                                    0x00F00000
#define    EMMCSDXC_PSTATE_WPSL_SHIFT                                     19
#define    EMMCSDXC_PSTATE_WPSL_MASK                                      0x00080000
#define    EMMCSDXC_PSTATE_CDPL_SHIFT                                     18
#define    EMMCSDXC_PSTATE_CDPL_MASK                                      0x00040000
#define    EMMCSDXC_PSTATE_CSS_SHIFT                                      17
#define    EMMCSDXC_PSTATE_CSS_MASK                                       0x00020000
#define    EMMCSDXC_PSTATE_CINS_SHIFT                                     16
#define    EMMCSDXC_PSTATE_CINS_MASK                                      0x00010000
#define    EMMCSDXC_PSTATE_BREN_SHIFT                                     11
#define    EMMCSDXC_PSTATE_BREN_MASK                                      0x00000800
#define    EMMCSDXC_PSTATE_BWEN_SHIFT                                     10
#define    EMMCSDXC_PSTATE_BWEN_MASK                                      0x00000400
#define    EMMCSDXC_PSTATE_RXACT_SHIFT                                    9
#define    EMMCSDXC_PSTATE_RXACT_MASK                                     0x00000200
#define    EMMCSDXC_PSTATE_WXACT_SHIFT                                    8
#define    EMMCSDXC_PSTATE_WXACT_MASK                                     0x00000100
#define    EMMCSDXC_PSTATE_RETUNE_REQ_SHIFT                               3
#define    EMMCSDXC_PSTATE_RETUNE_REQ_MASK                                0x00000008
#define    EMMCSDXC_PSTATE_DATACT_SHIFT                                   2
#define    EMMCSDXC_PSTATE_DATACT_MASK                                    0x00000004
#define    EMMCSDXC_PSTATE_DATINH_SHIFT                                   1
#define    EMMCSDXC_PSTATE_DATINH_MASK                                    0x00000002
#define    EMMCSDXC_PSTATE_CMDINH_SHIFT                                   0
#define    EMMCSDXC_PSTATE_CMDINH_MASK                                    0x00000001

#define EMMCSDXC_CTRL_OFFSET                                              0x00000028
#define EMMCSDXC_CTRL_TYPE                                                UInt32
#define EMMCSDXC_CTRL_RESERVED_MASK                                       0xF880E000
#define    EMMCSDXC_CTRL_WAKENRMV_SHIFT                                   26
#define    EMMCSDXC_CTRL_WAKENRMV_MASK                                    0x04000000
#define    EMMCSDXC_CTRL_WAKENINS_SHIFT                                   25
#define    EMMCSDXC_CTRL_WAKENINS_MASK                                    0x02000000
#define    EMMCSDXC_CTRL_WAKENIRQ_SHIFT                                   24
#define    EMMCSDXC_CTRL_WAKENIRQ_MASK                                    0x01000000
#define    EMMCSDXC_CTRL_ATLBOOTEN_SHIFT                                  22
#define    EMMCSDXC_CTRL_ATLBOOTEN_MASK                                   0x00400000
#define    EMMCSDXC_CTRL_BOOTEN_SHIFT                                     21
#define    EMMCSDXC_CTRL_BOOTEN_MASK                                      0x00200000
#define    EMMCSDXC_CTRL_SPIMODE_SHIFT                                    20
#define    EMMCSDXC_CTRL_SPIMODE_MASK                                     0x00100000
#define    EMMCSDXC_CTRL_BLKIRQ_SHIFT                                     19
#define    EMMCSDXC_CTRL_BLKIRQ_MASK                                      0x00080000
#define    EMMCSDXC_CTRL_RDWTCRTL_SHIFT                                   18
#define    EMMCSDXC_CTRL_RDWTCRTL_MASK                                    0x00040000
#define    EMMCSDXC_CTRL_CONTREQ_SHIFT                                    17
#define    EMMCSDXC_CTRL_CONTREQ_MASK                                     0x00020000
#define    EMMCSDXC_CTRL_BLKSTPREQ_SHIFT                                  16
#define    EMMCSDXC_CTRL_BLKSTPREQ_MASK                                   0x00010000
#define    EMMCSDXC_CTRL_HRESET_SHIFT                                     12
#define    EMMCSDXC_CTRL_HRESET_MASK                                      0x00001000
#define    EMMCSDXC_CTRL_SDVSEL_SHIFT                                     9
#define    EMMCSDXC_CTRL_SDVSEL_MASK                                      0x00000E00
#define    EMMCSDXC_CTRL_SDPWR_SHIFT                                      8
#define    EMMCSDXC_CTRL_SDPWR_MASK                                       0x00000100
#define    EMMCSDXC_CTRL_CDSD_SHIFT                                       7
#define    EMMCSDXC_CTRL_CDSD_MASK                                        0x00000080
#define    EMMCSDXC_CTRL_CDTL_SHIFT                                       6
#define    EMMCSDXC_CTRL_CDTL_MASK                                        0x00000040
#define    EMMCSDXC_CTRL_SDB_SHIFT                                        5
#define    EMMCSDXC_CTRL_SDB_MASK                                         0x00000020
#define    EMMCSDXC_CTRL_DMASEL_SHIFT                                     3
#define    EMMCSDXC_CTRL_DMASEL_MASK                                      0x00000018
#define    EMMCSDXC_CTRL_HSEN_SHIFT                                       2
#define    EMMCSDXC_CTRL_HSEN_MASK                                        0x00000004
#define    EMMCSDXC_CTRL_DXTW_SHIFT                                       1
#define    EMMCSDXC_CTRL_DXTW_MASK                                        0x00000002
#define    EMMCSDXC_CTRL_LEDCTL_SHIFT                                     0
#define    EMMCSDXC_CTRL_LEDCTL_MASK                                      0x00000001

#define EMMCSDXC_CTRL1_OFFSET                                             0x0000002C
#define EMMCSDXC_CTRL1_TYPE                                               UInt32
#define EMMCSDXC_CTRL1_RESERVED_MASK                                      0xF8F00018
#define    EMMCSDXC_CTRL1_DATRST_SHIFT                                    26
#define    EMMCSDXC_CTRL1_DATRST_MASK                                     0x04000000
#define    EMMCSDXC_CTRL1_CMDRST_SHIFT                                    25
#define    EMMCSDXC_CTRL1_CMDRST_MASK                                     0x02000000
#define    EMMCSDXC_CTRL1_RST_SHIFT                                       24
#define    EMMCSDXC_CTRL1_RST_MASK                                        0x01000000
#define    EMMCSDXC_CTRL1_DTCNT_SHIFT                                     16
#define    EMMCSDXC_CTRL1_DTCNT_MASK                                      0x000F0000
#define    EMMCSDXC_CTRL1_SDCLKSEL_SHIFT                                  8
#define    EMMCSDXC_CTRL1_SDCLKSEL_MASK                                   0x0000FF00
#define    EMMCSDXC_CTRL1_SDCLKSEL_UP_SHIFT                               6
#define    EMMCSDXC_CTRL1_SDCLKSEL_UP_MASK                                0x000000C0
#define    EMMCSDXC_CTRL1_CLKGENSEL_SHIFT                                 5
#define    EMMCSDXC_CTRL1_CLKGENSEL_MASK                                  0x00000020
#define    EMMCSDXC_CTRL1_SDCLKEN_SHIFT                                   2
#define    EMMCSDXC_CTRL1_SDCLKEN_MASK                                    0x00000004
#define    EMMCSDXC_CTRL1_ICLKSTB_SHIFT                                   1
#define    EMMCSDXC_CTRL1_ICLKSTB_MASK                                    0x00000002
#define    EMMCSDXC_CTRL1_ICLKEN_SHIFT                                    0
#define    EMMCSDXC_CTRL1_ICLKEN_MASK                                     0x00000001

#define EMMCSDXC_INTR_OFFSET                                              0x00000030
#define EMMCSDXC_INTR_TYPE                                                UInt32
#define EMMCSDXC_INTR_RESERVED_MASK                                       0xC8000000
#define    EMMCSDXC_INTR_CEATAERR_SHIFT                                   29
#define    EMMCSDXC_INTR_CEATAERR_MASK                                    0x20000000
#define    EMMCSDXC_INTR_TRESPERR_SHIFT                                   28
#define    EMMCSDXC_INTR_TRESPERR_MASK                                    0x10000000
#define    EMMCSDXC_INTR_TUNEERR_SHIFT                                    26
#define    EMMCSDXC_INTR_TUNEERR_MASK                                     0x04000000
#define    EMMCSDXC_INTR_ADMAERR_SHIFT                                    25
#define    EMMCSDXC_INTR_ADMAERR_MASK                                     0x02000000
#define    EMMCSDXC_INTR_CMDERROR_SHIFT                                   24
#define    EMMCSDXC_INTR_CMDERROR_MASK                                    0x01000000
#define    EMMCSDXC_INTR_IERR_SHIFT                                       23
#define    EMMCSDXC_INTR_IERR_MASK                                        0x00800000
#define    EMMCSDXC_INTR_DEBERR_SHIFT                                     22
#define    EMMCSDXC_INTR_DEBERR_MASK                                      0x00400000
#define    EMMCSDXC_INTR_DCRCERR_SHIFT                                    21
#define    EMMCSDXC_INTR_DCRCERR_MASK                                     0x00200000
#define    EMMCSDXC_INTR_DTOERR_SHIFT                                     20
#define    EMMCSDXC_INTR_DTOERR_MASK                                      0x00100000
#define    EMMCSDXC_INTR_CMDIDXERR_SHIFT                                  19
#define    EMMCSDXC_INTR_CMDIDXERR_MASK                                   0x00080000
#define    EMMCSDXC_INTR_CEBERR_SHIFT                                     18
#define    EMMCSDXC_INTR_CEBERR_MASK                                      0x00040000
#define    EMMCSDXC_INTR_CCRCERR_SHIFT                                    17
#define    EMMCSDXC_INTR_CCRCERR_MASK                                     0x00020000
#define    EMMCSDXC_INTR_CTOERR_SHIFT                                     16
#define    EMMCSDXC_INTR_CTOERR_MASK                                      0x00010000
#define    EMMCSDXC_INTR_ERRIRQ_SHIFT                                     15
#define    EMMCSDXC_INTR_ERRIRQ_MASK                                      0x00008000
#define    EMMCSDXC_INTR_BTIRQ_SHIFT                                      14
#define    EMMCSDXC_INTR_BTIRQ_MASK                                       0x00004000
#define    EMMCSDXC_INTR_BTACKRX_SHIFT                                    13
#define    EMMCSDXC_INTR_BTACKRX_MASK                                     0x00002000
#define    EMMCSDXC_INTR_RETUNE_EVENT_SHIFT                               12
#define    EMMCSDXC_INTR_RETUNE_EVENT_MASK                                0x00001000
#define    EMMCSDXC_INTR_INT_C_SHIFT                                      11
#define    EMMCSDXC_INTR_INT_C_MASK                                       0x00000800
#define    EMMCSDXC_INTR_INT_B_SHIFT                                      10
#define    EMMCSDXC_INTR_INT_B_MASK                                       0x00000400
#define    EMMCSDXC_INTR_INT_A_SHIFT                                      9
#define    EMMCSDXC_INTR_INT_A_MASK                                       0x00000200
#define    EMMCSDXC_INTR_CRDIRQ_SHIFT                                     8
#define    EMMCSDXC_INTR_CRDIRQ_MASK                                      0x00000100
#define    EMMCSDXC_INTR_CRDRMV_SHIFT                                     7
#define    EMMCSDXC_INTR_CRDRMV_MASK                                      0x00000080
#define    EMMCSDXC_INTR_CRDINS_SHIFT                                     6
#define    EMMCSDXC_INTR_CRDINS_MASK                                      0x00000040
#define    EMMCSDXC_INTR_BRRDY_SHIFT                                      5
#define    EMMCSDXC_INTR_BRRDY_MASK                                       0x00000020
#define    EMMCSDXC_INTR_BWRDY_SHIFT                                      4
#define    EMMCSDXC_INTR_BWRDY_MASK                                       0x00000010
#define    EMMCSDXC_INTR_DMAIRQ_SHIFT                                     3
#define    EMMCSDXC_INTR_DMAIRQ_MASK                                      0x00000008
#define    EMMCSDXC_INTR_BLKENT_SHIFT                                     2
#define    EMMCSDXC_INTR_BLKENT_MASK                                      0x00000004
#define    EMMCSDXC_INTR_TXDONE_SHIFT                                     1
#define    EMMCSDXC_INTR_TXDONE_MASK                                      0x00000002
#define    EMMCSDXC_INTR_CMDDONE_SHIFT                                    0
#define    EMMCSDXC_INTR_CMDDONE_MASK                                     0x00000001

#define EMMCSDXC_INTREN1_OFFSET                                           0x00000034
#define EMMCSDXC_INTREN1_TYPE                                             UInt32
#define EMMCSDXC_INTREN1_RESERVED_MASK                                    0xC8000000
#define    EMMCSDXC_INTREN1_CEATAERREN_SHIFT                              29
#define    EMMCSDXC_INTREN1_CEATAERREN_MASK                               0x20000000
#define    EMMCSDXC_INTREN1_TRESPERREN_SHIFT                              28
#define    EMMCSDXC_INTREN1_TRESPERREN_MASK                               0x10000000
#define    EMMCSDXC_INTREN1_TUNEERREN_SHIFT                               26
#define    EMMCSDXC_INTREN1_TUNEERREN_MASK                                0x04000000
#define    EMMCSDXC_INTREN1_ADMAEREN_SHIFT                                25
#define    EMMCSDXC_INTREN1_ADMAEREN_MASK                                 0x02000000
#define    EMMCSDXC_INTREN1_CMDERREN_SHIFT                                24
#define    EMMCSDXC_INTREN1_CMDERREN_MASK                                 0x01000000
#define    EMMCSDXC_INTREN1_ILIMERREN_SHIFT                               23
#define    EMMCSDXC_INTREN1_ILIMERREN_MASK                                0x00800000
#define    EMMCSDXC_INTREN1_DEBERREN_SHIFT                                22
#define    EMMCSDXC_INTREN1_DEBERREN_MASK                                 0x00400000
#define    EMMCSDXC_INTREN1_DCRCERREN_SHIFT                               21
#define    EMMCSDXC_INTREN1_DCRCERREN_MASK                                0x00200000
#define    EMMCSDXC_INTREN1_DTOERREN_SHIFT                                20
#define    EMMCSDXC_INTREN1_DTOERREN_MASK                                 0x00100000
#define    EMMCSDXC_INTREN1_CIDXERREN_SHIFT                               19
#define    EMMCSDXC_INTREN1_CIDXERREN_MASK                                0x00080000
#define    EMMCSDXC_INTREN1_CEBERREN_SHIFT                                18
#define    EMMCSDXC_INTREN1_CEBERREN_MASK                                 0x00040000
#define    EMMCSDXC_INTREN1_CMDCRCEN_SHIFT                                17
#define    EMMCSDXC_INTREN1_CMDCRCEN_MASK                                 0x00020000
#define    EMMCSDXC_INTREN1_CMDTOEN_SHIFT                                 16
#define    EMMCSDXC_INTREN1_CMDTOEN_MASK                                  0x00010000
#define    EMMCSDXC_INTREN1_FIXZ_SHIFT                                    15
#define    EMMCSDXC_INTREN1_FIXZ_MASK                                     0x00008000
#define    EMMCSDXC_INTREN1_BTIRQEN_SHIFT                                 14
#define    EMMCSDXC_INTREN1_BTIRQEN_MASK                                  0x00004000
#define    EMMCSDXC_INTREN1_BTACKRXEN_SHIFT                               13
#define    EMMCSDXC_INTREN1_BTACKRXEN_MASK                                0x00002000
#define    EMMCSDXC_INTREN1_RETUNE_EVENTEN_SHIFT                          12
#define    EMMCSDXC_INTREN1_RETUNE_EVENTEN_MASK                           0x00001000
#define    EMMCSDXC_INTREN1_INT_C_EN_SHIFT                                11
#define    EMMCSDXC_INTREN1_INT_C_EN_MASK                                 0x00000800
#define    EMMCSDXC_INTREN1_INT_B_EN_SHIFT                                10
#define    EMMCSDXC_INTREN1_INT_B_EN_MASK                                 0x00000400
#define    EMMCSDXC_INTREN1_INT_A_EN_SHIFT                                9
#define    EMMCSDXC_INTREN1_INT_A_EN_MASK                                 0x00000200
#define    EMMCSDXC_INTREN1_CIRQEN_SHIFT                                  8
#define    EMMCSDXC_INTREN1_CIRQEN_MASK                                   0x00000100
#define    EMMCSDXC_INTREN1_CRDRMVEN_SHIFT                                7
#define    EMMCSDXC_INTREN1_CRDRMVEN_MASK                                 0x00000080
#define    EMMCSDXC_INTREN1_CRDINSEN_SHIFT                                6
#define    EMMCSDXC_INTREN1_CRDINSEN_MASK                                 0x00000040
#define    EMMCSDXC_INTREN1_BUFRREN_SHIFT                                 5
#define    EMMCSDXC_INTREN1_BUFRREN_MASK                                  0x00000020
#define    EMMCSDXC_INTREN1_BUFWREN_SHIFT                                 4
#define    EMMCSDXC_INTREN1_BUFWREN_MASK                                  0x00000010
#define    EMMCSDXC_INTREN1_DMAIRQEN_SHIFT                                3
#define    EMMCSDXC_INTREN1_DMAIRQEN_MASK                                 0x00000008
#define    EMMCSDXC_INTREN1_BLKEN_SHIFT                                   2
#define    EMMCSDXC_INTREN1_BLKEN_MASK                                    0x00000004
#define    EMMCSDXC_INTREN1_TXDONEEN_SHIFT                                1
#define    EMMCSDXC_INTREN1_TXDONEEN_MASK                                 0x00000002
#define    EMMCSDXC_INTREN1_CMDDONEEN_SHIFT                               0
#define    EMMCSDXC_INTREN1_CMDDONEEN_MASK                                0x00000001

#define EMMCSDXC_INTREN2_OFFSET                                           0x00000038
#define EMMCSDXC_INTREN2_TYPE                                             UInt32
#define EMMCSDXC_INTREN2_RESERVED_MASK                                    0xC8000000
#define    EMMCSDXC_INTREN2_CEATAERRSEN_SHIFT                             29
#define    EMMCSDXC_INTREN2_CEATAERRSEN_MASK                              0x20000000
#define    EMMCSDXC_INTREN2_TRESPERRSEN_SHIFT                             28
#define    EMMCSDXC_INTREN2_TRESPERRSEN_MASK                              0x10000000
#define    EMMCSDXC_INTREN2_TUNEERRSEN_SHIFT                              26
#define    EMMCSDXC_INTREN2_TUNEERRSEN_MASK                               0x04000000
#define    EMMCSDXC_INTREN2_ADMASIGEN_SHIFT                               25
#define    EMMCSDXC_INTREN2_ADMASIGEN_MASK                                0x02000000
#define    EMMCSDXC_INTREN2_CMDSIGEN_SHIFT                                24
#define    EMMCSDXC_INTREN2_CMDSIGEN_MASK                                 0x01000000
#define    EMMCSDXC_INTREN2_ILIMSIGEN_SHIFT                               23
#define    EMMCSDXC_INTREN2_ILIMSIGEN_MASK                                0x00800000
#define    EMMCSDXC_INTREN2_DEBSIGEN_SHIFT                                22
#define    EMMCSDXC_INTREN2_DEBSIGEN_MASK                                 0x00400000
#define    EMMCSDXC_INTREN2_DCRCSIGEN_SHIFT                               21
#define    EMMCSDXC_INTREN2_DCRCSIGEN_MASK                                0x00200000
#define    EMMCSDXC_INTREN2_DTOSIGEN_SHIFT                                20
#define    EMMCSDXC_INTREN2_DTOSIGEN_MASK                                 0x00100000
#define    EMMCSDXC_INTREN2_CIDXSIGEN_SHIFT                               19
#define    EMMCSDXC_INTREN2_CIDXSIGEN_MASK                                0x00080000
#define    EMMCSDXC_INTREN2_CEBSIGEN_SHIFT                                18
#define    EMMCSDXC_INTREN2_CEBSIGEN_MASK                                 0x00040000
#define    EMMCSDXC_INTREN2_CMDCRCSIGEN_SHIFT                             17
#define    EMMCSDXC_INTREN2_CMDCRCSIGEN_MASK                              0x00020000
#define    EMMCSDXC_INTREN2_CMDTOSIGEN_SHIFT                              16
#define    EMMCSDXC_INTREN2_CMDTOSIGEN_MASK                               0x00010000
#define    EMMCSDXC_INTREN2_FIXZERO_SHIFT                                 15
#define    EMMCSDXC_INTREN2_FIXZERO_MASK                                  0x00008000
#define    EMMCSDXC_INTREN2_BTIRQSEN_SHIFT                                14
#define    EMMCSDXC_INTREN2_BTIRQSEN_MASK                                 0x00004000
#define    EMMCSDXC_INTREN2_BTACKRXSEN_SHIFT                              13
#define    EMMCSDXC_INTREN2_BTACKRXSEN_MASK                               0x00002000
#define    EMMCSDXC_INTREN2_RETUNE_EVENTSIGEN_SHIFT                       12
#define    EMMCSDXC_INTREN2_RETUNE_EVENTSIGEN_MASK                        0x00001000
#define    EMMCSDXC_INTREN2_INT_C_SIGEN_SHIFT                             11
#define    EMMCSDXC_INTREN2_INT_C_SIGEN_MASK                              0x00000800
#define    EMMCSDXC_INTREN2_INT_B_SIGEN_SHIFT                             10
#define    EMMCSDXC_INTREN2_INT_B_SIGEN_MASK                              0x00000400
#define    EMMCSDXC_INTREN2_INT_A_SIGEN_SHIFT                             9
#define    EMMCSDXC_INTREN2_INT_A_SIGEN_MASK                              0x00000200
#define    EMMCSDXC_INTREN2_CRDIRQEN_SHIFT                                8
#define    EMMCSDXC_INTREN2_CRDIRQEN_MASK                                 0x00000100
#define    EMMCSDXC_INTREN2_CRDRVMEN_SHIFT                                7
#define    EMMCSDXC_INTREN2_CRDRVMEN_MASK                                 0x00000080
#define    EMMCSDXC_INTREN2_CRDINSEN_SHIFT                                6
#define    EMMCSDXC_INTREN2_CRDINSEN_MASK                                 0x00000040
#define    EMMCSDXC_INTREN2_BUFRRDYEN_SHIFT                               5
#define    EMMCSDXC_INTREN2_BUFRRDYEN_MASK                                0x00000020
#define    EMMCSDXC_INTREN2_BUFWRDYEN_SHIFT                               4
#define    EMMCSDXC_INTREN2_BUFWRDYEN_MASK                                0x00000010
#define    EMMCSDXC_INTREN2_DMAIRQEN_SHIFT                                3
#define    EMMCSDXC_INTREN2_DMAIRQEN_MASK                                 0x00000008
#define    EMMCSDXC_INTREN2_BLKGAPEN_SHIFT                                2
#define    EMMCSDXC_INTREN2_BLKGAPEN_MASK                                 0x00000004
#define    EMMCSDXC_INTREN2_TXDONE_SHIFT                                  1
#define    EMMCSDXC_INTREN2_TXDONE_MASK                                   0x00000002
#define    EMMCSDXC_INTREN2_CMDDONE_SHIFT                                 0
#define    EMMCSDXC_INTREN2_CMDDONE_MASK                                  0x00000001

#define EMMCSDXC_ERRSTAT_OFFSET                                           0x0000003C
#define EMMCSDXC_ERRSTAT_TYPE                                             UInt32
#define EMMCSDXC_ERRSTAT_RESERVED_MASK                                    0x3F00FF60
#define    EMMCSDXC_ERRSTAT_PRESETEN_SHIFT                                31
#define    EMMCSDXC_ERRSTAT_PRESETEN_MASK                                 0x80000000
#define    EMMCSDXC_ERRSTAT_ASYNC_INTREN_SHIFT                            30
#define    EMMCSDXC_ERRSTAT_ASYNC_INTREN_MASK                             0x40000000
#define    EMMCSDXC_ERRSTAT_SAMPLECLOCKSEL_SHIFT                          23
#define    EMMCSDXC_ERRSTAT_SAMPLECLOCKSEL_MASK                           0x00800000
#define    EMMCSDXC_ERRSTAT_EXECTUNE_SHIFT                                22
#define    EMMCSDXC_ERRSTAT_EXECTUNE_MASK                                 0x00400000
#define    EMMCSDXC_ERRSTAT_DRVSTRESEL_SHIFT                              20
#define    EMMCSDXC_ERRSTAT_DRVSTRESEL_MASK                               0x00300000
#define    EMMCSDXC_ERRSTAT_EN1P8V_SHIFT                                  19
#define    EMMCSDXC_ERRSTAT_EN1P8V_MASK                                   0x00080000
#define    EMMCSDXC_ERRSTAT_UHSMODESEL_SHIFT                              16
#define    EMMCSDXC_ERRSTAT_UHSMODESEL_MASK                               0x00070000
#define    EMMCSDXC_ERRSTAT_NOCMD_SHIFT                                   7
#define    EMMCSDXC_ERRSTAT_NOCMD_MASK                                    0x00000080
#define    EMMCSDXC_ERRSTAT_CMDIDXERR_SHIFT                               4
#define    EMMCSDXC_ERRSTAT_CMDIDXERR_MASK                                0x00000010
#define    EMMCSDXC_ERRSTAT_CMDENDERR_SHIFT                               3
#define    EMMCSDXC_ERRSTAT_CMDENDERR_MASK                                0x00000008
#define    EMMCSDXC_ERRSTAT_CMDCRCERR_SHIFT                               2
#define    EMMCSDXC_ERRSTAT_CMDCRCERR_MASK                                0x00000004
#define    EMMCSDXC_ERRSTAT_CMDTOERR_SHIFT                                1
#define    EMMCSDXC_ERRSTAT_CMDTOERR_MASK                                 0x00000002
#define    EMMCSDXC_ERRSTAT_CMDNOEXEC_SHIFT                               0
#define    EMMCSDXC_ERRSTAT_CMDNOEXEC_MASK                                0x00000001

#define EMMCSDXC_CAPABILITIES1_OFFSET                                     0x00000040
#define EMMCSDXC_CAPABILITIES1_TYPE                                       UInt32
#define EMMCSDXC_CAPABILITIES1_RESERVED_MASK                              0x08100040
#define    EMMCSDXC_CAPABILITIES1_SLOTTYPE_SHIFT                          30
#define    EMMCSDXC_CAPABILITIES1_SLOTTYPE_MASK                           0xC0000000
#define    EMMCSDXC_CAPABILITIES1_ASYNCHIRQ_SHIFT                         29
#define    EMMCSDXC_CAPABILITIES1_ASYNCHIRQ_MASK                          0x20000000
#define    EMMCSDXC_CAPABILITIES1_SYSBUS64_SHIFT                          28
#define    EMMCSDXC_CAPABILITIES1_SYSBUS64_MASK                           0x10000000
#define    EMMCSDXC_CAPABILITIES1_V18_SHIFT                               26
#define    EMMCSDXC_CAPABILITIES1_V18_MASK                                0x04000000
#define    EMMCSDXC_CAPABILITIES1_V3_SHIFT                                25
#define    EMMCSDXC_CAPABILITIES1_V3_MASK                                 0x02000000
#define    EMMCSDXC_CAPABILITIES1_V33_SHIFT                               24
#define    EMMCSDXC_CAPABILITIES1_V33_MASK                                0x01000000
#define    EMMCSDXC_CAPABILITIES1_SUPRSM_SHIFT                            23
#define    EMMCSDXC_CAPABILITIES1_SUPRSM_MASK                             0x00800000
#define    EMMCSDXC_CAPABILITIES1_SDMA_SHIFT                              22
#define    EMMCSDXC_CAPABILITIES1_SDMA_MASK                               0x00400000
#define    EMMCSDXC_CAPABILITIES1_HSPEED_SHIFT                            21
#define    EMMCSDXC_CAPABILITIES1_HSPEED_MASK                             0x00200000
#define    EMMCSDXC_CAPABILITIES1_ADMA2_SHIFT                             19
#define    EMMCSDXC_CAPABILITIES1_ADMA2_MASK                              0x00080000
#define    EMMCSDXC_CAPABILITIES1_EXTBUSMED_SHIFT                         18
#define    EMMCSDXC_CAPABILITIES1_EXTBUSMED_MASK                          0x00040000
#define    EMMCSDXC_CAPABILITIES1_MAXBLK_SHIFT                            16
#define    EMMCSDXC_CAPABILITIES1_MAXBLK_MASK                             0x00030000
#define    EMMCSDXC_CAPABILITIES1_BCLK_SHIFT                              8
#define    EMMCSDXC_CAPABILITIES1_BCLK_MASK                               0x0000FF00
#define    EMMCSDXC_CAPABILITIES1_TOUT_SHIFT                              7
#define    EMMCSDXC_CAPABILITIES1_TOUT_MASK                               0x00000080
#define    EMMCSDXC_CAPABILITIES1_TOUTFREQ_SHIFT                          0
#define    EMMCSDXC_CAPABILITIES1_TOUTFREQ_MASK                           0x0000003F

#define EMMCSDXC_CAPABILITIES2_OFFSET                                     0x00000044
#define EMMCSDXC_CAPABILITIES2_TYPE                                       UInt32
#define EMMCSDXC_CAPABILITIES2_RESERVED_MASK                              0xFC001088
#define    EMMCSDXC_CAPABILITIES2_SPIBLOCKMODE_SHIFT                      25
#define    EMMCSDXC_CAPABILITIES2_SPIBLOCKMODE_MASK                       0x02000000
#define    EMMCSDXC_CAPABILITIES2_SPIMODE_CAP_SHIFT                       24
#define    EMMCSDXC_CAPABILITIES2_SPIMODE_CAP_MASK                        0x01000000
#define    EMMCSDXC_CAPABILITIES2_CLOCKMULT_SHIFT                         16
#define    EMMCSDXC_CAPABILITIES2_CLOCKMULT_MASK                          0x00FF0000
#define    EMMCSDXC_CAPABILITIES2_RETUNE_MODE_SHIFT                       14
#define    EMMCSDXC_CAPABILITIES2_RETUNE_MODE_MASK                        0x0000C000
#define    EMMCSDXC_CAPABILITIES2_USETUNE_SDR50_SHIFT                     13
#define    EMMCSDXC_CAPABILITIES2_USETUNE_SDR50_MASK                      0x00002000
#define    EMMCSDXC_CAPABILITIES2_TMRCNT_RETUNE_SHIFT                     8
#define    EMMCSDXC_CAPABILITIES2_TMRCNT_RETUNE_MASK                      0x00000F00
#define    EMMCSDXC_CAPABILITIES2_DRVR_TYPED_SHIFT                        6
#define    EMMCSDXC_CAPABILITIES2_DRVR_TYPED_MASK                         0x00000040
#define    EMMCSDXC_CAPABILITIES2_DRVR_TYPEC_SHIFT                        5
#define    EMMCSDXC_CAPABILITIES2_DRVR_TYPEC_MASK                         0x00000020
#define    EMMCSDXC_CAPABILITIES2_DRVR_TYPEA_SHIFT                        4
#define    EMMCSDXC_CAPABILITIES2_DRVR_TYPEA_MASK                         0x00000010
#define    EMMCSDXC_CAPABILITIES2_DDR50_SHIFT                             2
#define    EMMCSDXC_CAPABILITIES2_DDR50_MASK                              0x00000004
#define    EMMCSDXC_CAPABILITIES2_SDR104_SHIFT                            1
#define    EMMCSDXC_CAPABILITIES2_SDR104_MASK                             0x00000002
#define    EMMCSDXC_CAPABILITIES2_SDR50_SHIFT                             0
#define    EMMCSDXC_CAPABILITIES2_SDR50_MASK                              0x00000001

#define EMMCSDXC_MAX_A1_OFFSET                                            0x00000048
#define EMMCSDXC_MAX_A1_TYPE                                              UInt32
#define EMMCSDXC_MAX_A1_RESERVED_MASK                                     0xFF000000
#define    EMMCSDXC_MAX_A1_MAXA18_SHIFT                                   16
#define    EMMCSDXC_MAX_A1_MAXA18_MASK                                    0x00FF0000
#define    EMMCSDXC_MAX_A1_MAXA30_SHIFT                                   8
#define    EMMCSDXC_MAX_A1_MAXA30_MASK                                    0x0000FF00
#define    EMMCSDXC_MAX_A1_MAXA33_SHIFT                                   0
#define    EMMCSDXC_MAX_A1_MAXA33_MASK                                    0x000000FF

#define EMMCSDXC_MAX_A2_OFFSET                                            0x0000004C
#define EMMCSDXC_MAX_A2_TYPE                                              UInt32
#define EMMCSDXC_MAX_A2_RESERVED_MASK                                     0xFFFFFFFF

#define EMMCSDXC_CMDENTSTAT_OFFSET                                        0x00000050
#define EMMCSDXC_CMDENTSTAT_TYPE                                          UInt32
#define EMMCSDXC_CMDENTSTAT_RESERVED_MASK                                 0x0C00FF60
#define    EMMCSDXC_CMDENTSTAT_VSES_SHIFT                                 30
#define    EMMCSDXC_CMDENTSTAT_VSES_MASK                                  0xC0000000
#define    EMMCSDXC_CMDENTSTAT_CEAERR_SHIFT                               29
#define    EMMCSDXC_CMDENTSTAT_CEAERR_MASK                                0x20000000
#define    EMMCSDXC_CMDENTSTAT_TRERR_SHIFT                                28
#define    EMMCSDXC_CMDENTSTAT_TRERR_MASK                                 0x10000000
#define    EMMCSDXC_CMDENTSTAT_ADMAERR_SHIFT                              25
#define    EMMCSDXC_CMDENTSTAT_ADMAERR_MASK                               0x02000000
#define    EMMCSDXC_CMDENTSTAT_ACMDERR_SHIFT                              24
#define    EMMCSDXC_CMDENTSTAT_ACMDERR_MASK                               0x01000000
#define    EMMCSDXC_CMDENTSTAT_ILERR_SHIFT                                23
#define    EMMCSDXC_CMDENTSTAT_ILERR_MASK                                 0x00800000
#define    EMMCSDXC_CMDENTSTAT_DENDERR_SHIFT                              22
#define    EMMCSDXC_CMDENTSTAT_DENDERR_MASK                               0x00400000
#define    EMMCSDXC_CMDENTSTAT_DCRCERR_SHIFT                              21
#define    EMMCSDXC_CMDENTSTAT_DCRCERR_MASK                               0x00200000
#define    EMMCSDXC_CMDENTSTAT_DTOUTERR_SHIFT                             20
#define    EMMCSDXC_CMDENTSTAT_DTOUTERR_MASK                              0x00100000
#define    EMMCSDXC_CMDENTSTAT_CIDXERR_SHIFT                              19
#define    EMMCSDXC_CMDENTSTAT_CIDXERR_MASK                               0x00080000
#define    EMMCSDXC_CMDENTSTAT_CENDERR_SHIFT                              18
#define    EMMCSDXC_CMDENTSTAT_CENDERR_MASK                               0x00040000
#define    EMMCSDXC_CMDENTSTAT_CCRCERR_SHIFT                              17
#define    EMMCSDXC_CMDENTSTAT_CCRCERR_MASK                               0x00020000
#define    EMMCSDXC_CMDENTSTAT_CTOUTERR_SHIFT                             16
#define    EMMCSDXC_CMDENTSTAT_CTOUTERR_MASK                              0x00010000
#define    EMMCSDXC_CMDENTSTAT_NOFRCENT_SHIFT                             7
#define    EMMCSDXC_CMDENTSTAT_NOFRCENT_MASK                              0x00000080
#define    EMMCSDXC_CMDENTSTAT_IDXERR_SHIFT                               4
#define    EMMCSDXC_CMDENTSTAT_IDXERR_MASK                                0x00000010
#define    EMMCSDXC_CMDENTSTAT_EBITERR_SHIFT                              3
#define    EMMCSDXC_CMDENTSTAT_EBITERR_MASK                               0x00000008
#define    EMMCSDXC_CMDENTSTAT_CRCERR_SHIFT                               2
#define    EMMCSDXC_CMDENTSTAT_CRCERR_MASK                                0x00000004
#define    EMMCSDXC_CMDENTSTAT_TOUTERR_SHIFT                              1
#define    EMMCSDXC_CMDENTSTAT_TOUTERR_MASK                               0x00000002
#define    EMMCSDXC_CMDENTSTAT_AUTONOEX_SHIFT                             0
#define    EMMCSDXC_CMDENTSTAT_AUTONOEX_MASK                              0x00000001

#define EMMCSDXC_ADMAERR_OFFSET                                           0x00000054
#define EMMCSDXC_ADMAERR_TYPE                                             UInt32
#define EMMCSDXC_ADMAERR_RESERVED_MASK                                    0xFFFFFFF8
#define    EMMCSDXC_ADMAERR_ADMALERR_SHIFT                                2
#define    EMMCSDXC_ADMAERR_ADMALERR_MASK                                 0x00000004
#define    EMMCSDXC_ADMAERR_ADMAERR_SHIFT                                 0
#define    EMMCSDXC_ADMAERR_ADMAERR_MASK                                  0x00000003

#define EMMCSDXC_ADMAADDR0_OFFSET                                         0x00000058
#define EMMCSDXC_ADMAADDR0_TYPE                                           UInt32
#define EMMCSDXC_ADMAADDR0_RESERVED_MASK                                  0x00000000
#define    EMMCSDXC_ADMAADDR0_ADMAADDR0_SHIFT                             0
#define    EMMCSDXC_ADMAADDR0_ADMAADDR0_MASK                              0xFFFFFFFF

#define EMMCSDXC_PRESETVAL1_OFFSET                                        0x00000060
#define EMMCSDXC_PRESETVAL1_TYPE                                          UInt32
#define EMMCSDXC_PRESETVAL1_RESERVED_MASK                                 0x38003800
#define    EMMCSDXC_PRESETVAL1_DRVS_SEL_DFS_SHIFT                         30
#define    EMMCSDXC_PRESETVAL1_DRVS_SEL_DFS_MASK                          0xC0000000
#define    EMMCSDXC_PRESETVAL1_CLKGENSEL_DFS_SHIFT                        26
#define    EMMCSDXC_PRESETVAL1_CLKGENSEL_DFS_MASK                         0x04000000
#define    EMMCSDXC_PRESETVAL1_FREQ_SEL_DFS_SHIFT                         16
#define    EMMCSDXC_PRESETVAL1_FREQ_SEL_DFS_MASK                          0x03FF0000
#define    EMMCSDXC_PRESETVAL1_DRVS_SEL_INIT_SHIFT                        14
#define    EMMCSDXC_PRESETVAL1_DRVS_SEL_INIT_MASK                         0x0000C000
#define    EMMCSDXC_PRESETVAL1_CLKGENSEL_INIT_SHIFT                       10
#define    EMMCSDXC_PRESETVAL1_CLKGENSEL_INIT_MASK                        0x00000400
#define    EMMCSDXC_PRESETVAL1_FREQ_SEL_INIT_SHIFT                        0
#define    EMMCSDXC_PRESETVAL1_FREQ_SEL_INIT_MASK                         0x000003FF

#define EMMCSDXC_PRESETVAL2_OFFSET                                        0x00000064
#define EMMCSDXC_PRESETVAL2_TYPE                                          UInt32
#define EMMCSDXC_PRESETVAL2_RESERVED_MASK                                 0x38003800
#define    EMMCSDXC_PRESETVAL2_DRVS_SEL_SDR12_SHIFT                       30
#define    EMMCSDXC_PRESETVAL2_DRVS_SEL_SDR12_MASK                        0xC0000000
#define    EMMCSDXC_PRESETVAL2_CLKGENSEL_SDR12_SHIFT                      26
#define    EMMCSDXC_PRESETVAL2_CLKGENSEL_SDR12_MASK                       0x04000000
#define    EMMCSDXC_PRESETVAL2_FREQ_SEL_SDR12_SHIFT                       16
#define    EMMCSDXC_PRESETVAL2_FREQ_SEL_SDR12_MASK                        0x03FF0000
#define    EMMCSDXC_PRESETVAL2_DRVS_SEL_HS_SHIFT                          14
#define    EMMCSDXC_PRESETVAL2_DRVS_SEL_HS_MASK                           0x0000C000
#define    EMMCSDXC_PRESETVAL2_CLKGENSEL_HS_SHIFT                         10
#define    EMMCSDXC_PRESETVAL2_CLKGENSEL_HS_MASK                          0x00000400
#define    EMMCSDXC_PRESETVAL2_FREQ_SEL_HS_SHIFT                          0
#define    EMMCSDXC_PRESETVAL2_FREQ_SEL_HS_MASK                           0x000003FF

#define EMMCSDXC_PRESETVAL3_OFFSET                                        0x00000068
#define EMMCSDXC_PRESETVAL3_TYPE                                          UInt32
#define EMMCSDXC_PRESETVAL3_RESERVED_MASK                                 0x38003800
#define    EMMCSDXC_PRESETVAL3_DRVS_SEL_SDR50_SHIFT                       30
#define    EMMCSDXC_PRESETVAL3_DRVS_SEL_SDR50_MASK                        0xC0000000
#define    EMMCSDXC_PRESETVAL3_CLKGENSEL_SDR50_SHIFT                      26
#define    EMMCSDXC_PRESETVAL3_CLKGENSEL_SDR50_MASK                       0x04000000
#define    EMMCSDXC_PRESETVAL3_FREQ_SEL_SDR50_SHIFT                       16
#define    EMMCSDXC_PRESETVAL3_FREQ_SEL_SDR50_MASK                        0x03FF0000
#define    EMMCSDXC_PRESETVAL3_DRVS_SEL_SDR25_SHIFT                       14
#define    EMMCSDXC_PRESETVAL3_DRVS_SEL_SDR25_MASK                        0x0000C000
#define    EMMCSDXC_PRESETVAL3_CLKGENSEL_SDR25_SHIFT                      10
#define    EMMCSDXC_PRESETVAL3_CLKGENSEL_SDR25_MASK                       0x00000400
#define    EMMCSDXC_PRESETVAL3_FREQ_SEL_SDR25_SHIFT                       0
#define    EMMCSDXC_PRESETVAL3_FREQ_SEL_SDR25_MASK                        0x000003FF

#define EMMCSDXC_PRESETVAL4_OFFSET                                        0x0000006C
#define EMMCSDXC_PRESETVAL4_TYPE                                          UInt32
#define EMMCSDXC_PRESETVAL4_RESERVED_MASK                                 0x38003800
#define    EMMCSDXC_PRESETVAL4_DRVS_SEL_DDR50_SHIFT                       30
#define    EMMCSDXC_PRESETVAL4_DRVS_SEL_DDR50_MASK                        0xC0000000
#define    EMMCSDXC_PRESETVAL4_CLKGENSEL_DDR50_SHIFT                      26
#define    EMMCSDXC_PRESETVAL4_CLKGENSEL_DDR50_MASK                       0x04000000
#define    EMMCSDXC_PRESETVAL4_FREQ_SEL_DDR50_SHIFT                       16
#define    EMMCSDXC_PRESETVAL4_FREQ_SEL_DDR50_MASK                        0x03FF0000
#define    EMMCSDXC_PRESETVAL4_DRVS_SEL_SDR25_SHIFT                       14
#define    EMMCSDXC_PRESETVAL4_DRVS_SEL_SDR25_MASK                        0x0000C000
#define    EMMCSDXC_PRESETVAL4_CLKGENSEL_SDR25_SHIFT                      10
#define    EMMCSDXC_PRESETVAL4_CLKGENSEL_SDR25_MASK                       0x00000400
#define    EMMCSDXC_PRESETVAL4_FREQ_SEL_SDR25_SHIFT                       0
#define    EMMCSDXC_PRESETVAL4_FREQ_SEL_SDR25_MASK                        0x000003FF

#define EMMCSDXC_BOOTTIMEOUT_OFFSET                                       0x00000070
#define EMMCSDXC_BOOTTIMEOUT_TYPE                                         UInt32
#define EMMCSDXC_BOOTTIMEOUT_RESERVED_MASK                                0x00000000
#define    EMMCSDXC_BOOTTIMEOUT_BOOTDATATIMEOUTCTRVALUE_SHIFT             0
#define    EMMCSDXC_BOOTTIMEOUT_BOOTDATATIMEOUTCTRVALUE_MASK              0xFFFFFFFF

#define EMMCSDXC_DBGSEL_OFFSET                                            0x00000074
#define EMMCSDXC_DBGSEL_TYPE                                              UInt32
#define EMMCSDXC_DBGSEL_RESERVED_MASK                                     0xFFFFFFFE
#define    EMMCSDXC_DBGSEL_DBGSEL_SHIFT                                   0
#define    EMMCSDXC_DBGSEL_DBGSEL_MASK                                    0x00000001

#define EMMCSDXC_SBUSCTRL_OFFSET                                          0x000000E0
#define EMMCSDXC_SBUSCTRL_TYPE                                            UInt32
#define EMMCSDXC_SBUSCTRL_RESERVED_MASK                                   0x808880C8
#define    EMMCSDXC_SBUSCTRL_BEPWR_CTRL_SHIFT                             24
#define    EMMCSDXC_SBUSCTRL_BEPWR_CTRL_MASK                              0x7F000000
#define    EMMCSDXC_SBUSCTRL_INTRPINSEL_SHIFT                             20
#define    EMMCSDXC_SBUSCTRL_INTRPINSEL_MASK                              0x00700000
#define    EMMCSDXC_SBUSCTRL_CLKPINSEL_SHIFT                              16
#define    EMMCSDXC_SBUSCTRL_CLKPINSEL_MASK                               0x00070000
#define    EMMCSDXC_SBUSCTRL_BUSW_PRESET_SHIFT                            8
#define    EMMCSDXC_SBUSCTRL_BUSW_PRESET_MASK                             0x00007F00
#define    EMMCSDXC_SBUSCTRL_NUMIRQPINS_SHIFT                             4
#define    EMMCSDXC_SBUSCTRL_NUMIRQPINS_MASK                              0x00000030
#define    EMMCSDXC_SBUSCTRL_NUMCLKPINS_SHIFT                             0
#define    EMMCSDXC_SBUSCTRL_NUMCLKPINS_MASK                              0x00000007

#define EMMCSDXC_SPI_INT_OFFSET                                           0x000000F0
#define EMMCSDXC_SPI_INT_TYPE                                             UInt32
#define EMMCSDXC_SPI_INT_RESERVED_MASK                                    0xFFFFFFFE
#define    EMMCSDXC_SPI_INT_SPISUP_SHIFT                                  0
#define    EMMCSDXC_SPI_INT_SPISUP_MASK                                   0x00000001

#define EMMCSDXC_HCVERSIRQ_OFFSET                                         0x000000FC
#define EMMCSDXC_HCVERSIRQ_TYPE                                           UInt32
#define EMMCSDXC_HCVERSIRQ_RESERVED_MASK                                  0x0000FF00
#define    EMMCSDXC_HCVERSIRQ_VENDVER_SHIFT                               24
#define    EMMCSDXC_HCVERSIRQ_VENDVER_MASK                                0xFF000000
#define    EMMCSDXC_HCVERSIRQ_SPECVER_SHIFT                               16
#define    EMMCSDXC_HCVERSIRQ_SPECVER_MASK                                0x00FF0000
#define    EMMCSDXC_HCVERSIRQ_SIRQ_SHIFT                                  0
#define    EMMCSDXC_HCVERSIRQ_SIRQ_MASK                                   0x000000FF

#define EMMCSDXC_CORECTRL_OFFSET                                          0x00008000
#define EMMCSDXC_CORECTRL_TYPE                                            UInt32
#define EMMCSDXC_CORECTRL_RESERVED_MASK                                   0xFFFFFFF0
#define    EMMCSDXC_CORECTRL_CD_PINCTRL_SHIFT                             3
#define    EMMCSDXC_CORECTRL_CD_PINCTRL_MASK                              0x00000008
#define    EMMCSDXC_CORECTRL_STOP_HCLK_SHIFT                              2
#define    EMMCSDXC_CORECTRL_STOP_HCLK_MASK                               0x00000004
#define    EMMCSDXC_CORECTRL_RESET_SHIFT                                  1
#define    EMMCSDXC_CORECTRL_RESET_MASK                                   0x00000002
#define    EMMCSDXC_CORECTRL_EN_SHIFT                                     0
#define    EMMCSDXC_CORECTRL_EN_MASK                                      0x00000001

#define EMMCSDXC_CORESTAT_OFFSET                                          0x00008004
#define EMMCSDXC_CORESTAT_TYPE                                            UInt32
#define EMMCSDXC_CORESTAT_RESERVED_MASK                                   0xFFFFFE0C
#define    EMMCSDXC_CORESTAT_LED_SHIFT                                    8
#define    EMMCSDXC_CORESTAT_LED_MASK                                     0x00000100
#define    EMMCSDXC_CORESTAT_BUS_VOLT_SHIFT                               5
#define    EMMCSDXC_CORESTAT_BUS_VOLT_MASK                                0x000000E0
#define    EMMCSDXC_CORESTAT_BUS_PWR_SHIFT                                4
#define    EMMCSDXC_CORESTAT_BUS_PWR_MASK                                 0x00000010
#define    EMMCSDXC_CORESTAT_WP_SHIFT                                     1
#define    EMMCSDXC_CORESTAT_WP_MASK                                      0x00000002
#define    EMMCSDXC_CORESTAT_CD_SW_SHIFT                                  0
#define    EMMCSDXC_CORESTAT_CD_SW_MASK                                   0x00000001

#define EMMCSDXC_COREIMR_OFFSET                                           0x00008008
#define EMMCSDXC_COREIMR_TYPE                                             UInt32
#define EMMCSDXC_COREIMR_RESERVED_MASK                                    0xFFFFFFFC
#define    EMMCSDXC_COREIMR_DAT1_SHIFT                                    1
#define    EMMCSDXC_COREIMR_DAT1_MASK                                     0x00000002
#define    EMMCSDXC_COREIMR_IP_SHIFT                                      0
#define    EMMCSDXC_COREIMR_IP_MASK                                       0x00000001

#define EMMCSDXC_COREISR_OFFSET                                           0x0000800C
#define EMMCSDXC_COREISR_TYPE                                             UInt32
#define EMMCSDXC_COREISR_RESERVED_MASK                                    0xFFFFFFFC
#define    EMMCSDXC_COREISR_DAT1_SHIFT                                    1
#define    EMMCSDXC_COREISR_DAT1_MASK                                     0x00000002
#define    EMMCSDXC_COREISR_IP_SHIFT                                      0
#define    EMMCSDXC_COREISR_IP_MASK                                       0x00000001

#define EMMCSDXC_COREIMSR_OFFSET                                          0x00008010
#define EMMCSDXC_COREIMSR_TYPE                                            UInt32
#define EMMCSDXC_COREIMSR_RESERVED_MASK                                   0xFFFFFFFC
#define    EMMCSDXC_COREIMSR_DAT1_SHIFT                                   1
#define    EMMCSDXC_COREIMSR_DAT1_MASK                                    0x00000002
#define    EMMCSDXC_COREIMSR_IP_SHIFT                                     0
#define    EMMCSDXC_COREIMSR_IP_MASK                                      0x00000001

#define EMMCSDXC_COREDBG1_OFFSET                                          0x00008014
#define EMMCSDXC_COREDBG1_TYPE                                            UInt32
#define EMMCSDXC_COREDBG1_RESERVED_MASK                                   0x00000000
#define    EMMCSDXC_COREDBG1_OBSERVABLE_SHIFT                             0
#define    EMMCSDXC_COREDBG1_OBSERVABLE_MASK                              0xFFFFFFFF

#define EMMCSDXC_COREGPO_MASK_OFFSET                                      0x00008018
#define EMMCSDXC_COREGPO_MASK_TYPE                                        UInt32
#define EMMCSDXC_COREGPO_MASK_RESERVED_MASK                               0xFFFFFE00
#define    EMMCSDXC_COREGPO_MASK_ERROR_INT_SHIFT                          8
#define    EMMCSDXC_COREGPO_MASK_ERROR_INT_MASK                           0x00000100
#define    EMMCSDXC_COREGPO_MASK_CARD_INT_SHIFT                           7
#define    EMMCSDXC_COREGPO_MASK_CARD_INT_MASK                            0x00000080
#define    EMMCSDXC_COREGPO_MASK_DMA_INT_SHIFT                            6
#define    EMMCSDXC_COREGPO_MASK_DMA_INT_MASK                             0x00000040
#define    EMMCSDXC_COREGPO_MASK_TRANS_COMP_SHIFT                         5
#define    EMMCSDXC_COREGPO_MASK_TRANS_COMP_MASK                          0x00000020
#define    EMMCSDXC_COREGPO_MASK_CMD_COMP_SHIFT                           4
#define    EMMCSDXC_COREGPO_MASK_CMD_COMP_MASK                            0x00000010
#define    EMMCSDXC_COREGPO_MASK_INT_TOARM_SHIFT                          3
#define    EMMCSDXC_COREGPO_MASK_INT_TOARM_MASK                           0x00000008
#define    EMMCSDXC_COREGPO_MASK_BUS_POW_SHIFT                            2
#define    EMMCSDXC_COREGPO_MASK_BUS_POW_MASK                             0x00000004
#define    EMMCSDXC_COREGPO_MASK_LED_ON_SHIFT                             1
#define    EMMCSDXC_COREGPO_MASK_LED_ON_MASK                              0x00000002
#define    EMMCSDXC_COREGPO_MASK_HIGH_SHIFT                               0
#define    EMMCSDXC_COREGPO_MASK_HIGH_MASK                                0x00000001

#endif /* __BRCM_RDB_EMMCSDXC_H__ */


